 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Freescale Semiconductor Technical Data Document Number: MPC8349EEC Rev. 10, 07/2007 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications The MPC8349E PowerQUICCTM II Pro is a next generation PowerQUICC II integrated host processor. The MPC8349E contains a PowerPCTM processor core built on Power ArchitectureTM technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349E PowerQUICCTM II Pro Integrated Host Processor Reference Manual. To locate published errata or updates for this document, refer to the MPC8349E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. NOTE The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and later versions (for orderable part numbers ending in A or B), see the MPC8349EA PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by This Document," for silicon revision level determination. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet: Three-Speed Ethernet, MII Management . 21 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 System Design Information . . . . . . . . . . . . . . . . . . . 79 Document Revision History . . . . . . . . . . . . . . . . . . . 83 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. (c) Freescale Semiconductor, Inc., 2005-2007. All rights reserved. Overview 1 Overview This section provides a high-level overview of the MPC8349E features. Figure 1 shows the major functional units within the MPC8349E. DDR SDRAM ROM SDRAM IRQs DDR Memory Controller Local Bus Controller Programmable Interrupt Controller Security Engine SPI Serial I2C USB0 USB1 GPIO Serial Peripheral Interface DUART I2C Interfaces USB Hi-Speed Host Device General Purpose I/O 64/32b PCI Controller Sequencer SEQ 0/32b PCI Controller DMA Controller TSEC 10/100/1Gb TSEC 10/100/1Gb PCI1 PCI2 Arbiter Bus Monitor e300 Core 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache Coherent System Bus DMA MII, GMII, TBI, RTBI, RGMII MII, GMII, TBI, RTBI, RGMII Figure 1. MPC8349E Block Diagram Major features of the MPC8349E are as follows: * Embedded PowerPC e300 processor core; operates at up to 667 MHz -- High-performance, superscalar processor core -- Floating-point, integer, load/store, system register, and branch processing units -- 32-Kbyte instruction cache, 32-Kbyte data cache -- Lockable portion of L1 cache -- Dynamic power management -- Software-compatible with the other Freescale processor families that implement Power Architecture technology * Double data rate, DDR SDRAM memory controller -- Programmable timing for DDR-1 SDRAM -- 32- or 64-bit data interface, up to 333-MHz data rate -- Four banks of memory, each up to 1 Gbyte -- DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports -- Full error checking and correction (ECC) support -- Page mode support (up to 16 simultaneous open pages) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 2 Freescale Semiconductor Overview * * -- Contiguous or discontiguous memory mapping -- Read-modify-write support -- Sleep mode for self-refresh SDRAM -- Auto refresh -- On-the-fly power management using CKE -- Registered DIMM support -- 2.5-V SSTL2 compatible I/O Dual three-speed (10/100/1000) Ethernet controllers (TSECs) -- Dual controllers designed to comply with IEEE 802.3(R), 802.3u(R), 820.3x(R), 802.3z(R), 802.3ac(R) standards -- Ethernet physical interfaces: - 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex - 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex -- Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models -- 9.6-Kbyte jumbo frame support -- RMON statistics support -- Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module -- MII management interface for control and status -- Programmable CRC generation and checking Dual PCI interfaces -- Designed to comply with PCI Specification Revision 2.2 -- Data bus width options: - Dual 32-bit data PCI interfaces operating at up to 66 MHz - Single 64-bit data PCI interface operating at up to 66 MHz -- PCI 3.3-V compatible -- PCI host bridge capabilities on both interfaces -- PCI agent mode on PCI1 interface -- PCI-to-memory and memory-to-PCI streaming -- Memory prefetching of PCI read accesses and support for delayed read transactions -- Posting of processor-to-PCI and PCI-to-memory writes -- On-chip arbitration supporting five masters on PCI1, three masters on PCI2 -- Accesses to all PCI address spaces -- Parity supported -- Selectable hardware-enforced coherency -- Address translation units for address mapping between host and peripheral -- Dual address cycle for target -- Internal configuration registers accessible from PCI MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 3 Overview * * Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i(R), iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): -- Public key execution unit (PKEU) : - RSA and Diffie-Hellman algorithms - Programmable field size up to 2048 bits - Elliptic curve cryptography - F2m and F(p) modes - Programmable field size up to 511 bits -- Data encryption standard (DES) execution unit (DEU) - DES and 3DES algorithms - Two key (K1, K2) or three key (K1, K2, K3) for 3DES - ECB and CBC modes for both DES and 3DES -- Advanced encryption standard unit (AESU) - Implements the Rijndael symmetric-key cipher - Key lengths of 128, 192, and 256 bits - ECB, CBC, CCM, and counter (CTR) modes -- ARC four execution unit (AFEU) - Stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key -- Message digest execution unit (MDEU) - SHA with 160- or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- Random number generator (RNG) -- Four crypto-channels, each supporting multi-command descriptor chains - Static and/or dynamic assignment of crypto-execution units through an integrated controller - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Universal serial bus (USB) dual role controller -- USB on-the-go mode with both device and host functionality -- Complies with USB specification Rev. 2.0 -- Can operate as a stand-alone USB device - One upstream facing port - Six programmable USB endpoints -- Can operate as a stand-alone USB host controller - USB root hub with one downstream-facing port - Enhanced host controller interface (EHCI) compatible - High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 4 Freescale Semiconductor Overview * * * * * -- External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) Universal serial bus (USB) multi-port host controller -- Can operate as a stand-alone USB host controller - USB root hub with one or two downstream-facing ports - Enhanced host controller interface (EHCI) compatible - Complies with USB Specification Rev. 2.0 -- High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations -- Direct connection to a high-speed device without an external hub -- External PHY with serial and low-pin count (ULPI) interfaces Local bus controller (LBC) -- Multiplexed 32-bit address and data operating at up to 133 MHz -- Four chip selects support four external slaves -- Up to eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller -- Three protocol engines on a per chip select basis: - General-purpose chip select machine (GPCM) - Three user-programmable machines (UPMs) - Dedicated single data rate SDRAM controller -- Parity support -- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) -- Functional and programming compatibility with the MPC8260 interrupt controller -- Support for 8 external and 35 internal discrete interrupt sources -- Support for 1 external (optional) and 7 internal machine checkstop interrupt sources -- Programmable highest priority request -- Four groups of interrupts with programmable priority -- External and internal interrupts directed to host processor -- Redirects interrupts to external INTA pin in core disable mode. -- Unique vector number for each interrupt source Dual industry-standard I2C interfaces -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus -- System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 5 Overview * * * * * * -- Four independent virtual channels -- Concurrent execution across multiple channels with programmable bandwidth control -- All channels accessible to local core and remote PCI masters -- Misaligned transfer capability -- Data chaining and direct mode -- Interrupt on completed segment and chain DUART -- Two 4-wire interfaces (RxD, TxD, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral interface (SPI) for master or slave General-purpose parallel I/O (GPIO) -- 64 parallel I/O pins multiplexed on various chip interfaces System timers -- Periodic interrupt timer -- Real-time clock -- Software watchdog timer -- Eight general-purpose timers Designed to comply with IEEE Std. 1149.1TM, JTAG boundary scan Integrated PCI bus and SDRAM clock generation MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 6 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8349E. The MPC8349E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD AVDD GVDD LVDD I2C, OV DD MVIN MVREF LVIN OVIN OVIN TSTG Max Value -0.3 to 1.32 -0.3 to 1.32 -0.3 to 3.63 -0.3 to 3.63 -0.3 to 3.63 -0.3 to (GV DD + 0.3) -0.3 to (GV DD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (OV DD + 0.3) -0.3 to (OV DD + 0.3) -55 to 150 Unit V V V V V V V V V V C 2, 5 2, 5 4, 5 3, 5 6 Notes Table 1 provides the absolute maximum ratings. Core supply voltage PLL supply voltage DDR DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals Local bus, DUART, CLKIN, system control and power management, I2C, and JTAG signals PCI Storage temperature range 1 Notes: Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 Caution: MV must not exceed GV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 Caution: OV must not exceed OV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 Caution: LV must not exceed LV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5 (M,L,O)V and MV IN REF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6 OV on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as IN shown in Figure 3. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 7 Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8349E. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage DDR DRAM I/O supply voltage Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage 1 Symbol VDD AVDD GVDD LVDD1 LVDD2 OVDD Recommended Value 1.2 V 60 mV 1.2 V 60 mV 2.5 V 125 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV Unit V V V V V V Notes 1 1 Note: GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349E. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 8 Freescale Semiconductor Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349E for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform -3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) 4 ns (Max) Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Local bus interface utilities signals PCI signals (not including PCI output clocks) PCI output clocks (including PCI_SYNC_OUT) DDR signal TSEC/10/100 signals DUART, system control, GPIO signals I2C, JTAG, USB Output Impedance () 40 25 40 18 40 40 40 GVDD = 2.5 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V, LVDD = 2.5/3.3 V Supply Voltage OVDD = 3.3 V 2.2 Power Sequencing MPC8349E does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 9 Power Characteristics 3 Power Characteristics Table 4. MPC8349E Power Dissipation1 Core Frequency (MHz) TBGA 333 CSB Frequency (MHz) 333 166 400 266 133 450 300 150 500 333 166 533 266 133 Typical2, 3 Maximum4 The estimated typical power dissipation for the MPC8349E device is shown in Table 4. Typical at TJ = 65 2.0 1.8 2.1 1.9 2.3 2.1 2.4 2.2 2.4 2.2 Unit 3.0 2.8 3.0 2.9 3.2 3.0 3.3 3.1 3.3 3.1 3.2 2.9 3.3 3.1 3.5 3.2 3.6 3.4 3.6 3.4 W W W W W W W W W W 2 The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of T J = 105C, and a Dhrystone benchmark application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T target, and I/O A power. 4 Maximum power is based on a voltage of V DD = 1.2 V, worst case process, a junction temperature of TJ= 105C, and an artificial smoke test. 1 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 10 Freescale Semiconductor Power Characteristics Table 5 shows the estimated typical I/O power dissipation for MPC8349E. Table 5. MPC8349E Typical I/O Power Dissipation Interface DDR I/O 65% utilization 2.5 V Rs = 20 Rt = 50 2 pair of clocks Parameter 200 MHz, 32 bits 200 MHz, 64 bits 266 MHz, 32 bits 266 MHz, 64 bits 300 MHz, 32 bits 300 MHz, 64 bits 333 MHz, 32 bits 333 MHz, 64 bits 400 MHz, 32 bits 400 MHz, 64 bits PCI I/O load = 30 pF 33 MHz, 64 bits 66 MHz, 64 bits 33 MHz, 32 bits 66 MHz, 32 bits Local bus I/O load = 25 pF 133 MHz, 32 bits 83 MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O load = 25 pF MII GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O 0.01 0.2 0.01 GVDD (1.8 V) -- -- -- -- -- -- -- -- -- -- 0.08 0.14 0.04 0.07 0.27 0.17 0.14 0.11 0.01 0.06 0.04 W W W W W W W W W W W W W W Multiply by 2 if using 2 ports. Multiply by number of interfaces used. Multiply by 2 if using 2 ports. GVDD (2.5 V) 0.42 0.55 0.5 0.66 0.54 0.7 0.58 0.76 OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit W W W W W W W W Comments MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 11 Clock Input Timing 4 4.1 Clock Input Timing DC Electrical Characteristics Table 6. CLKIN DC Timing Specifications Parameter Condition -- -- 0 V VIN OVDD 0 V VIN 0.5 V or OVDD - 0.5 V VIN OV DD 0.5 V VIN OVDD - 0.5 V Symbol VIH VIL IIN IIN IIN Min 2.7 -0.3 -- -- -- Max OVDD + 0.3 0.4 10 10 50 Unit V V A A A This section provides the clock input DC and AC electrical characteristics for the MPC8349E. Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349E. Input high voltage Input low voltage CLKIN input current PCI_SYNC_IN input current PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8349E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the MPC8349E. Table 7. CLKIN AC Timing Specifications Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tKHK/tCLKIN -- Min -- 15 0.6 40 -- Typical -- -- 1.0 -- -- Max 66 -- 2.3 60 150 Unit MHz ns ns % ps Notes 1 -- 2 3 4, 5 Notes: 1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter--short term and long term--and is guaranteed by design. 5. The CLKIN/PCI_CLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 12 Freescale Semiconductor RESET Initialization 5 RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8349E. 5.1 RESET DC Electrical Characteristics Table 8. RESET Pins DC Electrical Characteristics1 Characteristic Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8349E. Input high voltage Input low voltage Input current Output high voltage2 Output low voltage Output low voltage Notes: 1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins. 5.2 RESET AC Electrical Characteristics Table 9. RESET Initialization Timing Specifications Parameter/Condition Min 32 32 32 512 16 4 Max -- -- -- -- -- -- Unit tPCI_SYNC_IN tCLKIN tPCI_SYNC_IN tPCI_SYNC_IN tPCI_SYNC_IN tCLKIN Notes 1 2 1 1 1 2 Table 9 provides the reset initialization AC timing specifications of the MPC8349E. Required assertion time of HRESET or SRESET (input) to activate reset flow Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8349E is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8349E is in PCI agent mode HRESET/SRESET assertion (output) HRESET negation to SRESET negation (output) Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349E is in PCI host mode Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349E is in PCI agent mode 4 -- tPCI_SYNC_IN 1 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 13 RESET Initialization Table 9. RESET Initialization Timing Specifications (continued) Parameter/Condition Input hold time for POR configuration signals with respect to negation of HRESET Time for the MPC8349E to turn off POR configuration signals with respect to the assertion of HRESET Time for the MPC8349E to turn on POR configuration signals with respect to the negation of HRESET Min 0 -- 1 Max -- 4 -- Unit ns ns tPCI_SYNC_IN 3 1, 3 Notes Notes: 1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349E PowerQUICCTM II Pro Integrated Host Processor Family Reference Manual. 2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349E PowerQUICCTM II Pro Integrated Host Processor Family Reference Manual. 3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. Table 10 lists the PLL and DLL lock times. Table 10. PLL and DLL Lock Times Parameter/Condition PLL lock times DLL lock times Min -- 7680 Max 100 122,880 Unit s csb_clk cycles 1, 2 Notes Notes: 1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, "Clocking." MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 14 Freescale Semiconductor DDR SDRAM 6 DDR SDRAM NOTE The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and earlier versions see the MPC8349EA PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by This Document," for silicon revision level determination. This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8349E. 6.1 DDR SDRAM DC Electrical Characteristics Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8349E. Table 11. DDR SDRAM DC Electrical Characteristics Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) MV REF input leakage current Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL IVREF Min 2.375 0.49 x GVDD MVREF - 0.04 MVREF + 0.18 -0.3 -10 -15.2 15.2 -- Max 2.625 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.18 10 -- -- 5 Unit V V V V V A mA mA A 4 Notes 1 2 3 Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MV REF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GV DD. Table 12 provides the DDR capacitance. Table 12. DDR SDRAM Capacitance Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 15 DDR SDRAM 6.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR SDRAM Input AC Timing Specifications Table 13. DDR SDRAM Input AC Timing Specifications Table 13 provides the input AC timing specifications for the DDR SDRAM interface. At recommended operating conditions with GVDD of 2.5 V 5%. Parameter AC input low voltage AC input high voltage MDQS--MDQ/MECC input skew per byte 333 MHz 266 MHz Symbol VIL VIH tDISKEW Min -- MVREF + 0.31 -- Max MVREF - 0.31 GVDD + 0.3 750 1125 Unit V V ps Notes 1 Note: 1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <= 7) or ECC (MECC[{0...7}] if n = 8). 6.2.2 DDR SDRAM Output AC Timing Specifications Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the DDR SDRAM interface. Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode At recommended operating conditions with GVDD of 2.5 V 5%. Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD 333 MHz 266 MHz 200 MHz ADDR/CMD output setup with respect to MCK 333 MHz 266 MHz 200 MHz ADDR/CMD output hold with respect to MCK 333 MHz 266 MHz 200 MHz MCS(n) output setup with respect to MCK 333 MHz 266 MHz 200 MHz Symbol1 tMCK tAOSKEW Min 6 -1000 -1100 -1200 Max 10 200 300 400 -- Unit ns ps Notes 2 3 tDDKHAS 2.8 3.45 4.6 tDDKHAX 2.0 2.65 3.8 tDDKHCS 2.8 3.45 4.6 ns 4 -- ns 4 -- ns 4 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 16 Freescale Semiconductor DDR SDRAM Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued) At recommended operating conditions with GVDD of 2.5 V 5%. Parameter MCS(n) output hold with respect to MCK 333 MHz 266 MHz 200 MHz MCK to MDQS 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output setup with respect to MDQS 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 333 MHz 266 MHz 200 MHz MDQS preamble start MDQS epilogue end Symbol1 tDDKHCX Min Max -- Unit ns Notes 4 2.0 2.65 3.8 tDDKHMH -0.9 -1.1 -1.2 tDDKHDS, tDDKLDS 900 900 1200 tDDKHDX, tDDKLDX 900 900 1200 tDDKHMP tDDKLME -0.25 x tMCK - 0.9 -0.9 -0.25 x tMCK + 0.3 0.3 ns ns 7 7 -- ps 6 0.3 0.5 0.6 -- ps 6 ns 5 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the clock control register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of MCK. 4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8349E PowerQUICCTM II Pro Integrated Host Processor Family Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. 6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8349E. 7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8349E. Note that tDDKHMP follows the symbol conventions described in note 1. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 17 DDR SDRAM Figure 4 shows the DDR SDRAM output timing for address skew with respect to any MCK. MCK[n] MCK[n] tMCK tAOSKEWmax) ADDR/CMD CMD NOOP tAOSKEW(min) ADDR/CMD CMD NOOP Figure 4. Timing Diagram for tAOSKEW Measurement Figure 5 provides the AC test load for the DDR bus. Output Z0 = 50 RL = 50 OVDD/2 Figure 5. DDR AC Test Load Table 15 shows the DDR SDRAM measurement conditions. Table 15. DDR SDRAM Measurement Conditions Symbol VTH VOUT Notes: 1. Data input threshold measurement point. 2. Data output measurement point. DDR MVREF 0.31 V 0.5 x GVDD Unit V V Notes 1 2 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 18 Freescale Semiconductor DDR SDRAM Figure 6 shows the DDR SDRAM output timing diagram for source synchronous mode. MCK[n] MCK[n] tMCK tDDKHAS,tDDKHCS tDDKHAX, tDDKHCX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode Table 16 provides approximate delay information that can be expected for the address and command signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL. These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. Table 16. Expected Delays for Address/Command Load 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF) + 40 pF compensation capacitor 36 devices (108 pF) + 80 pF compensation capacitor Delay 3.0 3.6 5.0 5.2 Unit ns ns ns ns MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 19 DUART 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8349E. 7.1 DUART DC Electrical Characteristics Table 17. DUART DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OV DD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V Table 17 provides the DC electrical characteristics for the DUART interface of the MPC8349E. High-level input voltage Low-level input voltage Input current (0.8 V VIN 2 V) High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A 7.2 DUART AC Electrical Specifications Table 18. DUART AC Timing Specifications Parameter Value 256 >1,000,000 16 Unit baud baud -- 1 2 Notes Table 18 provides the AC timing parameters for the DUART interface of the MPC8349E. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 20 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and MII management. 8.1 Three-Speed Ethernet Controller (TSEC)-- GMII/MII/TBI/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to the gigabit media independent interface (GMII), the media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V, and the RGMII and RTBI interfaces can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification, Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3, "Ethernet Management Interface Electrical Characteristics." 8.1.1 TSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 19 and Table 20. The potential applied to the input of a GMII, MII, TBI, RGMII, or RTBI receiver may exceed the potential of the receiver power supply (that is, a RGMII driver powered from a 3.6-V supply driving VOH into a RGMII receiver powered from a 2.5-V supply). Tolerance for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 19. GMII/TBI and MII DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD2 VOH VOL VIH VIL IIH IIL IOH = -4.0 mA IOL = 4.0 mA -- -- VIN1 = LVDD VIN 1= Conditions -- LVDD = Min LVDD = Min -- -- Min 2.97 2.40 GND 2.0 -0.3 -- -600 Max 3.63 LVDD + 0.3 0.50 LVDD + 0.3 0.90 40 -- Unit V V V V V A A GND Notes: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 21 Ethernet: Three-Speed Ethernet, MII Management Table 20. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL IOH = -1.0 mA IOL = 1.0 mA -- -- VIN1 = VIN1 = Conditions -- LVDD = Min LVDD = Min LVDD = Min LVDD = Min LVDD GND Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- -15 Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 10 -- Unit V V V V V A A Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.2.1.1 GMII Transmit AC Timing Specifications Table 21. GMII Transmit AC Timing Specifications Table 21 provides the GMII transmit AC timing specifications. At recommended operating conditions with LVDD /OVDD of 3.3 V 10%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, VIL(min) to V IH(max) GTX_CLK clock fall time, VIH(max) to VIL(min) GTX_CLK125 clock period GTX_CLK125 reference clock duty cycle measured at LVDD/2 Symbol1 tGTX tGTXH/tGTX tGTKHDX tGTXR tGTXF tG125 2 Min -- 43.75 0.5 -- -- -- 45 Typ 8.0 -- -- -- -- 8.0 -- Max -- 56.25 5.0 1.0 1.0 -- 55 Unit ns % ns ns ns ns % tG125H/tG125 Notes: 1. The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 22 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 7 shows the GMII transmit AC timing diagram. tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTXF tGTXR Figure 7. GMII Transmit AC Timing Diagram 8.2.1.2 GMII Receive AC Timing Specifications Table 22. GMII Receive AC Timing Specifications Table 22 provides the GMII receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V 10%. Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise, V IL(min) to VIH(max) RX_CLK clock fall time, V IH(max) to VIL(min) Symbol1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF Min -- 40 2.0 0.5 -- -- Typ 8.0 -- -- -- -- -- Max -- 60 -- -- 1.0 1.0 Unit ns % ns ns ns ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t GRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 23 Ethernet: Three-Speed Ethernet, MII Management Figure 8 shows the GMII receive AC timing diagram. G tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR Figure 8. GMII Receive AC Timing Diagram 8.2.2 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.2.1 MII Transmit AC Timing Specifications Table 23. MII Transmit AC Timing Specifications Table 23 provides the MII transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V 10%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) TX_CLK data clock fall VIH(max) to VIL(min) Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF Min -- -- 35 1 1.0 1.0 Typ 400 40 -- 5 -- -- Max -- -- 65 15 4.0 4.0 Unit ns ns % ns ns ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of t MTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 24 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 9 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 9. MII Transmit AC Timing Diagram 8.2.2.2 MII Receive AC Timing Specifications Table 24. MII Receive AC Timing Specifications Table 24 provides the MII receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V 10%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min) Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF Min -- -- 35 10.0 10.0 1.0 1.0 Typ 400 40 -- -- -- -- -- Max -- -- 65 -- -- 4.0 4.0 Unit ns ns % ns ns ns ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 10 provides the AC test load for TSEC. Output Z0 = 50 RL = 50 OVDD/2 Figure 10. TSEC AC Test Load MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 25 Ethernet: Three-Speed Ethernet, MII Management Figure 11 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRXF Valid Data tMRDVKH tMRDXKH tMRXR Figure 11. MII Receive AC Timing Diagram 8.2.3 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.3.1 TBI Transmit AC Timing Specifications Table 25. TBI Transmit AC Timing Specifications Table 25 provides the TBI transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V 10%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise, V IL(min) to VIH(max) GTX_CLK clock fall time, V IH(max) to VIL(min) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle Symbol1 tTTX tTTXH/tTTX tTTKHDX tTTXR tTTXF tG1252 tG125H/tG125 Min -- 40 1.0 -- -- -- 45 Typ 8.0 -- -- -- -- 8.0 -- Max -- 60 5.0 1.0 1.0 -- 55 Unit ns % ns ns ns ns ns Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 26 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 12 shows the TBI transmit AC timing diagram. tTTX GTX_CLK tTTXH TXD[7:0] TX_EN TX_ER tTTXF tTTXR tTTKHDX Figure 12. TBI Transmit AC Timing Diagram 8.2.3.2 TBI Receive AC Timing Specifications Table 26. TBI Receive AC Timing Specifications Table 26 provides the TBI receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V 10%. Parameter/Condition PMA_RX_CLK clock period PMA_RX_CLK skew RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising PMA_RX_CLK RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising PMA_RX_CLK RX_CLK clock rise time VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min) Symbol1 tTRX tSKTRX tTRXH/tTRX tTRDVKH2 tTRDXKH2 tTRXR tTRXF Min Typ 16.0 Max Unit ns 7.5 40 2.5 1.5 0.7 0.7 -- -- -- -- -- -- 8.5 60 -- -- 2.4 2.4 ns % ns ns ns ns Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX). 2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 27 Ethernet: Three-Speed Ethernet, MII Management Figure 13 shows the TBI receive AC timing diagram. tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Even RCG Odd RCG tTRXR Figure 13. TBI Receive AC Timing Diagram 8.2.4 RGMII and RTBI AC Timing Specifications Table 27. RGMII and RTBI AC Timing Specifications Table 27 presents the RGMII and RTBI AC timing specifications. At recommended operating conditions with LVDD of 2.5 V 5%. Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration 3 4, 5 3, 5 2 Symbol1 tSKRGT tSKRGT tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG126 tG125H/tG125 Min -0.5 1.0 7.2 45 40 -- -- -- 47 Typ -- -- 8.0 50 50 -- -- 8.0 -- Max 0.5 2.8 8.8 55 60 0.75 0.75 -- 53 Unit ns ns ns % % ns ns ns % Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle Notes: 1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT). 2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned. 5. Duty cycle reference is LVDD/2. 6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 28 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 14 shows the RBMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CLK (At PHY) Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 29 Ethernet:Three-Speed Ethernet, MII Management 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to the MII management interface signals management data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII, RGMII, TBI and RTBI are specified in Section 8.1, "Three-Speed Ethernet Controller (TSEC)-- GMII/MII/TBI/RGMII/RTBI Electrical Characteristics." 8.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 2.5 or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 28 and Table 29. Table 28. MII Management DC Electrical Characteristics Powered at 2.5 V Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL Conditions -- IOH = -1.0 mA IOL = 1.0 mA -- -- VIN1 LVDD = Min LVDD = Min LVDD = Min LVDD = Min = LVDD Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- -15 Max 2.63 LVDD + 0.3 0.40 -- 0.70 10 -- Unit V V V V V A A VIN = LVDD Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. Table 29. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL LVDD = Max LVDD = Max IOH = -1.0 mA IOL = 1.0 mA -- -- VIN = 2.1 V VIN = 0.5 V 1 Conditions -- LVDD = Min LVDD = Min Min 2.97 2.10 GND 2.00 -- -- -600 Max 3.63 LV DD + 0.3 0.50 -- 0.80 40 -- Unit V V V V V A A Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 30 Freescale Semiconductor Ethernet:Three-Speed Ethernet, MII Management 8.3.2 MII Management AC Electrical Specifications Table 30. MII Management AC Timing Specifications Table 30 provides the MII management AC timing specifications. At recommended operating conditions with LVDD is 3.3 V 10% or 2.5 V 5%. Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Symbol1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min -- -- 32 10 5 0 -- -- Typ 2.5 400 -- -- -- -- -- -- Max -- -- -- 170 -- -- 10 10 Unit MHz ns ns ns ns ns ns ns Notes 2 3 Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of 333 MHz, the delay is 58 ns). Figure 15 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 15. MII Management Interface Timing Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 31 USB 9 9.1 USB USB DC Electrical Characteristics Table 31. USB DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OV DD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V This section provides the AC and DC electrical specifications for the USB interface of the MPC8349E. Table 31 provides the DC electrical characteristics for the USB interface. High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A 9.2 USB AC Electrical Specifications Table 32. USB General Timing Parameters Parameter Symbol1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 -- 2 Max -- -- -- 7 -- Unit ns ns ns ns ns Notes 2-5 2-5 2-5 2-5 2-5 Table 32 describes the general timing parameters of the USB interface of the MPC8349E. USB clock cycle time Input setup to USB clock--all inputs Input hold to USB clock--all inputs USB clock to output valid--all outputs Output hold from USB clock--all outputs Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 32 Freescale Semiconductor USB Figure 16 and Figure 17 provide the AC test load and signals for the USB, respectively. Output Z0 = 50 RL = 50 OVDD /2 Figure 16. USB AC Test Load USB0_CLK/USB1_CLK/DR_CLK tUSIVKH Input Signals tUSIXKH tUSKHOV Output Signals: tUSKHOX Figure 17. USB Signals MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 33 Local Bus 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8349E. 10.1 Local Bus DC Electrical Characteristics Table 33. Local Bus DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OV DD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V Table 33 provides the DC electrical characteristics for the local bus interface. High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A 10.2 Local Bus AC Electrical Specification Table 34. Local Bus General Timing Parameters--DLL On Parameter Symbol1 tLBK tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHLR tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOX1 Min 7.5 1.5 2.2 1.0 1.0 1.5 3 2.5 -- -- -- -- 1 Max -- -- -- -- -- -- -- -- 4.5 4.5 4.5 4.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 3 Notes 2 3, 4 3, 4 3, 4 3, 4 5 6 7 Table 34 and Table 35 describe the general timing parameters of the local bus interface of the MPC8349E. Local bus cycle time Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 34 Freescale Semiconductor Local Bus Table 34. Local Bus General Timing Parameters--DLL On (continued) Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOX2 tLBKHOZ Min 1 -- Max -- 3.8 Unit ns ns Notes 3 8 Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD output pins. 8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. Table 35. Local Bus General Timing Parameters--DLL Bypass9 Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Symbol1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 Min 15 7 1.0 1.5 3 2.5 Max -- -- -- -- -- -- Unit ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 35 Local Bus Table 35. Local Bus General Timing Parameters--DLL Bypass9 (continued) Parameter Local bus clock to output valid Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOV tLBKHOZ Min -- -- Max 3 4 Unit ns ns Notes 3 8 Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.the 7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals to the load on the LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 18 provides the AC test load for the local bus. Output Z0 = 50 RL = 50 OVDD/2 Figure 18. Local Bus C Test Load MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 36 Freescale Semiconductor Local Bus Figure 19 through Figure 24 show the local bus signals. LSYNC_IN tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV Output (Address) Signal: LAD[0:31] tLBKHLR LALE tLBOTOT tLBKHOZ tLBKHOX tLBKHOV tLBIXKH tLBKHOV tLBKHOZ tLBKHOX Figure 19. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) LCLK[n] tLBIVKH tLBIXKH tLBIVKH tLBIXKH Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output Signals: LAD[0:31]/LDP[0:3] LALE tLBKHOV tLBKHOV tLBKHOZ tLBKLOV tLBOTOT Figure 20. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 37 Local Bus LSYNC_IN T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled) LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 38 Freescale Semiconductor Local Bus LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 39 Local Bus LSYNC_IN T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 40 Freescale Semiconductor JTAG 11 JTAG This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8349E. 11.1 JTAG DC Electrical Characteristics Table 36 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8349E. Table 36. JTAG interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min OV DD - 0.3 -0.3 Max OVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V 11.2 JTAG AC Timing Specifications This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8349E. Table 37 provides the JTAG AC timing specifications as defined in Figure 26 through Figure 29. Table 37. JTAG AC Timing Specifications (Independent of CLKIN)1 At recommended operating conditions (see Table 2). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Symbol2 fJTG t JTG tJTKHKL tJTGR, tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV Min 0 30 15 0 25 4 4 Max 33.3 -- -- 2 -- -- -- Unit MHz ns ns ns ns ns Notes 3 4 ns 10 10 -- -- ns 2 2 11 11 5 4 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 41 JTAG Table 37. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued) At recommended operating conditions (see Table 2). Parameter Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol2 Min Max Unit ns Notes tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ 2 2 -- -- ns 5 2 2 19 9 5, 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 25). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. Figure 25 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349E. Output Z0 = 50 RL = 50 OVDD/2 Figure 25. AC Test Load for the JTAG Interface Figure 26 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OV DD/2) VM VM tJTGR tJTGF Figure 26. JTAG Clock Input Timing Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 42 Freescale Semiconductor JTAG Figure 27 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OV DD/2) VM Figure 27. TRST Timing Diagram Figure 28 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 28. Boundary-Scan Timing Diagram Figure 29 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 29. Test Access Port Timing Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 43 I2C 12 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8349E. 12.1 I2C DC Electrical Characteristics Table 38. I2C DC Electrical Characteristics Table 38 provides the DC electrical characteristics for the I2C interface of the MPC8349E. At recommended operating conditions with OVDD of 3.3 V 10%. Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) Capacitance for each I/O pin Symbol VIH VIL VOL tI2KLKV tI2KHKL II CI Min 0.7 x OV DD -0.3 0 20 + 0.1 x CB 0 -10 -- Max OVDD + 0.3 0.3 x OV DD 0.2 x OV DD 250 50 10 10 Unit V V V ns ns A pF Notes 1 2 3 4 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8349E Integrated Host Processor Reference Manual, for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off. 12.2 I2C AC Electrical Specifications Table 39 provides the AC timing parameters for the I2C interface of the MPC8349E. Note that all values refer to VIH(min) and VIL(max) levels (see Table 38). Table 39. I2C AC Electrical Specifications Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 -- 02 Max 400 -- -- -- -- -- -- 0.93 Unit kHz s s s s ns s MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 44 Freescale Semiconductor I2C Table 39. I2C AC Electrical Specifications (continued) Parameter Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol1 tI2CR tI2CF tI2PVKH tI2KHDX VNL VNH Min 20 + 0.1 Cb4 20 + 0.1 Cb 0.6 1.3 0.1 x OV DD 0.2 x OV DD 4 Max 300 300 -- -- -- -- Unit ns ns s s V V Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8349E provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Figure 30 provides the AC test load for the I2C. Output Z0 = 50 RL = 50 OVDD/2 Figure 30. I2C AC Test Load Figure 31 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL 2 tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF tI2CH Sr tI2SVKH tI2PVKH P S Figure 31. I C Bus AC Timing Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 45 PCI 13 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8349E. 13.1 PCI DC Electrical Characteristics Table 40. PCI DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL VIN Test Condition VOUT VOH (min) or VOUT VOL (max) 1= Table 40 provides the DC electrical characteristics for the PCI interface of the MPC8349E. Min 2 -0.3 -- OV DD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V High-level input voltage Low-level input voltage Input current High-level output voltage Low-level output voltage 0 V or V IN = OVDD OVDD = min, IOH = -100 A OVDD = min, IOL = 100 A Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1. 13.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8349E. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8349E is configured as a host or agent device. Table 41 provides the PCI AC timing specifications at 66 MHz. Table 41. PCI AC Timing Specifications at 66 MHz1 Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock REQ64 to PORESET setup time Symbol2 tPCKHOV Min -- 1 -- 3.0 0 5 Max 6.0 -- 14 -- -- -- Unit ns ns ns ns ns clocks Notes 3 3 3, 4 3, 5 3, 5 6 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCRVRH MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 46 Freescale Semiconductor PCI Table 41. PCI AC Timing Specifications at 66 MHz1 (continued) Parameter PORESET to REQ64 hold time Symbol2 tPCRHRX Min 0 Max 50 Unit ns Notes 6 Notes: 1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a description of M66EN. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 3. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Input timings are measured at the pin. 6. The setup and hold time is with respect to the rising edge of PORESET. Table 42 provides the PCI AC timing specifications at 33 MHz. Table 42. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock REQ64 to PORESET setup time PORESET to REQ64 hold time Symbol1 tPCKHOV Min -- 2 -- 3.0 0 5 0 Max 11 -- 14 -- -- -- 50 Unit ns ns ns ns ns clocks ns Notes 2 2 2, 3 2, 4 2, 4 5 5 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCRVRH tPCRHRX Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 5. The setup and hold time is with respect to the rising edge of PORESET. Figure 32 provides the AC test load for PCI. Output Z0 = 50 RL = 50 OVDD/2 Figure 32. PCI AC Test Load MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 47 PCI Figure 33 shows the PCI input AC timing diagram. CLK tPCIVKH tPCIXKH Input Figure 33. PCI Input AC Timing Diagram Figure 34 shows the PCI output AC timing diagram. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 34. PCI Output AC Timing Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 48 Freescale Semiconductor Timers 14 Timers This section describes the DC and AC electrical specifications for the timers. 14.1 Timer DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the MPC8349E timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 43. Timer DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V 14.2 Timer AC Timing Specifications Table 44. Timers Input AC Timing Specifications1 Characteristic Symbol2 tTIWID Min 20 Unit ns Table 44 provides the timer input and output AC timing specifications. Timers inputs--minimum pulse width Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 49 GPIO 15 GPIO This section describes the DC and AC electrical specifications for the GPIO. 15.1 GPIO DC Electrical Characteristics Table 45. GPIO DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V Table 45 provides the DC electrical characteristics for the MPC8349E GPIO. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage 15.2 GPIO AC Timing Specifications Table 46. GPIO Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 46 provides the GPIO input and output AC timing specifications. GPIO inputs--minimum pulse width Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 50 Freescale Semiconductor IPIC 16 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins. 16.1 IPIC DC Electrical Characteristics Table 47. IPIC DC Electrical Characteristics1 Characteristic Symbol VIH VIL IIN VOL VOL IOL = 8.0 mA IOL = 3.2 mA -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 5 0.5 0.4 Unit V V A V V 2 2 Notes Table 47 provides the DC electrical characteristics for the external interrupt pins. Input high voltage Input low voltage Input current Output low voltage Output low voltage Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT. 2. IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins. 16.2 IPIC AC Timing Specifications Table 48. IPIC Input AC Timing Specifications1 Characteristic Symbol2 tPICWID Min 20 Unit ns Table 48 provides the IPIC input and output AC timing specifications. IPIC inputs--minimum pulse width Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 51 SPI 17 SPI This section describes the SPI DC and AC electrical specifications. 17.1 SPI DC Electrical Characteristics Table 49. SPI DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V Table 49 provides the SPI DC electrical characteristics. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage 17.2 SPI AC Timing Specifications Table 50. SPI AC Timing Specifications1 Characteristic Symbol2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH tNEIVKH tNEIXKH 2 4 0 4 2 0.5 8 Min Max 6 Unit ns ns ns ns ns ns ns ns Table 50 provides the SPI input and output AC timing specifications. SPI outputs valid--Master mode (internal clock) delay SPI outputs hold--Master mode (internal clock) delay SPI outputs valid--Slave mode (external clock) delay SPI outputs hold--Slave mode (external clock) delay SPI inputs--Master mode (internal clock input setup time SPI inputs--Master mode (internal clock input hold time SPI inputs--Slave mode (external clock) input setup time SPI inputs--Slave mode (external clock) input hold time Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal. Timings are measured at the pin. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 52 Freescale Semiconductor SPI Figure 35 provides the AC test load for the SPI. Output Z0 = 50 RL = 50 OVDD/2 Figure 35. SPI AC Test Load Figure 36 and Figure 37 represent the AC timings from Table 50. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 36 shows the SPI timings in slave mode (external clock). SPICLK (Input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOX Note: The clock edge is selectable on SPI. Figure 36. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 37 shows the SPI timings in master mode (internal clock). SPICLK (Output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOX Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 53 Package and Pin Listings 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8349E is available in a tape ball grid array (TBGA). See Section 18.1, "Package Parameters for the MPC8349E TBGA" and Section 18.2, "Mechanical Dimensions for the MPC8349E TBGA." 18.1 Package Parameters for the MPC8349E TBGA The package parameters are provided in the following list. The package type is 35 mm x 35 mm, 672 tape ball grid array (TBGA). Package outline 35 mm x 35 mm Interconnects 672 Pitch 1.00 mm Module height (typical) 1.46 mm Solder balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 54 Freescale Semiconductor Package and Pin Listings 18.2 Mechanical Dimensions for the MPC8349E TBGA Figure 38 shows the mechanical dimensions and bottom surface nomenclature for the MPC8349E, 672-TBGA package. Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. Figure 38. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349E TBGA MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 55 Package and Pin Listings 18.3 Pinout Listings Table 51. MPC8349E (TBGA) Pinout Listing Signal Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) Pin Type Power Supply Notes Table 51 provides the pin-out listing for the MPC8349E, 672 TBGA package. PCI1_INTA/IRQ_OUT PCI1_RESET_OUT PCI1_AD[31:0] B34 C33 G30, G32, G34, H31, H32, H33, H34, J29, J32, J33, L30, K31, K33, K34, L33, L34, P34, R29, R30, R33, R34, T31, T32, T33, U31, U34, V31, V32, V33, V34, W33, W34 J30, M31, P33, T34 P32 M32 N29 M34 N31 N30 J31 N34 N33 D32 D34 E34, F32, G29 C34 D33 E33 F31, F33 W32 AA33, AA34, AB31, AB32, AB33, AB34, AC29, AC31, AC33, AC34, AD30, AD32, AD33, AD34, AE29, AE30, AH32, AH33, AH34, AM33, AJ31, AJ32, AJ33, AJ34, AK32, AK33, AK34, AM34, AL33, AL34, AK31, AH30 AC32, AE32, AH31, AL32 AG34 O O I/O OV DD OV DD OV DD 2 PCI1_C/BE[3:0] PCI1_PAR PCI1_FRAME PCI1_TRDY PCI1_IRDY PCI1_STOP PCI1_DEVSEL PCI1_IDSEL PCI1_SERR PCI1_PERR PCI1_REQ[0] PCI1_REQ[1]/CPCI1_HS_ES PCI1_REQ[2:4] PCI1_GNT0 PCI1_GNT1/CPCI1_HS_LED PCI1_GNT2/CPCI1_HS_ENUM PCI1_GNT[3:4] PCI2_RESET_OUT/GPIO2[0] PCI2_AD[31:0]/PCI1[63:32] I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I I/O O O O I/O I/O OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 5 5 5 5 5 5 5 PCI2_C/BE[3:0]/PCI1_C/BE[7:4] PCI2_PAR/PCI1_PAR64 I/O I/O OV DD OV DD MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 56 Freescale Semiconductor Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal PCI2_FRAME/GPIO2[1] PCI2_TRDY/GPIO2[2] PCI2_IRDY/GPIO2[3] PCI2_STOP/GPIO2[4] PCI2_DEVSEL/GPIO2[5] PCI2_SERR/PCI1_ACK64 PCI2_PERR/PCI1_REQ64 PCI2_REQ[0:2]/GPIO2[6:8] PCI2_GNT[0:2]/GPIO2[9:11] M66EN AE33 AF32 AE34 AF34 AF33 AG33 AG32 Y32, Y34, AA32 Y31, Y33, AA31 A19 DDR SDRAM Memory Interface MDQ[0:63] D5, A3, C3, D3, C4, B3, C2, D4, D2, E5, G2, H6, E4, F3, G4, G3, H1, J2, L6, M6, H2, K6, L2, M4, N2, P4, R2, T4, P6, P3, R1, T2, AB5, AA3, AD6, AE4, AB4, AC2, AD3, AE6, AE3, AG4, AK5, AK4, AE2, AG6, AK3, AK2, AL2, AL1, AM5, AP5, AM2, AN1, AP4, AN5, AJ7, AN7, AM8, AJ9, AP6, AL7, AL9, AN8 W4, W3, Y3, AA6, T1 U1 Y1, Y6 B1, F1, K1, R4, AD4, AJ1, AP3, AP7, Y4 B2, F5, J1, P2, AC1, AJ2, AN4, AL8, W2 AD1, AA5 W1, U4, T3, R3, P1, M1, N1, L3, L1, K2, Y2, K3, J3, AP2, AN6 AF1 AF4 AG3 AG2, AG1, AK1, AL4 H3, G1 U2, F4, AM3, V3, F2, AN3 U3, E3, AN2, V4, E1, AM4 I/O GVDD Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes 5 5 5 5 5 5 5 MECC[0:4]/MSRCID[0:4] MECC[5]/MDVAL MECC[6:7] MDM[0:8] MDQS[0:8] MBA[0:1] MA[0:14] MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] I/O I/O I/O O I/O O O O O O O O O O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD 3 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 57 Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes Pins Reserved for Future DDR2 (They should be left unconnected for MPC8349E) MODT[0:3] MBA[2] SPARE1 SPARE2 AH3, AJ5, AH1, AJ4 H4 AA1 AB1 Local Bus Controller Interface LAD[0:31] AM13, AP13, AL14, AM14, AN14, AP14, AK15, AJ15, AM15, AN15, AP15, AM16, AL16, AN16, AP16, AL17, AM17, AP17, AK17, AP18, AL18, AM18, AN18, AP19, AN19, AM19, AP20, AK19, AN20, AL20, AP21, AN21 AM21 AP22 AN22 AM22 AK21, AP23, AN23, AP24, AK22 AN24, AL23, AP25, AN25 AK23, AP26, AL24, AM25 AN26 AK24 AP27 AL25 AJ24 AN27 AP28 AL26 AM27 AN28, AK26, AP29 AM12 AJ10 General Purpose I/O Timers GPIO1[0]/GTM1_TIN1/GTM2_TIN2 F24 I/O OV DD I/O OV DD -- -- -- -- -- -- -- -- 8 6 LDP[0]/CKSTOP_OUT LDP[1]/CKSTOP_IN LDP[2] LDP[3] LA[27:31] LCS[0:3] LWE[0:3]/LSDDQM[0:3]/LBS[0:3] LBCTL LALE LGPL0/LSDA10/cfg_reset_source0 LGPL1/LSDWE/cfg_reset_source1 LGPL2/LSDRAS/LOE LGPL3/LSDCAS/cfg_reset_source2 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5/cfg_clkin_div LCKE LCLK[0:2] LSYNC_OUT LSYNC_IN I/O I/O I/O I/O O O O O O I/O I/O O I/O I/O I/O O O O I OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 58 Freescale Semiconductor Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal GPIO1[1]/GTM1_TGATE1/ GTM2_TGATE2 GPIO1[2]/GTM1_TOUT1 GPIO1[3]/GTM1_TIN2/GTM2_TIN1 GPIO1[4]/GTM1_TGATE2/ GTM2_TGATE1 GPIO1[5]/GTM1_TOUT2/ GTM2_TOUT1 GPIO1[6]/GTM1_TIN3/GTM2_TIN4 GPIO1[7]/GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/GTM1_TOUT3 GPIO1[9]/GTM1_TIN4/GTM2_TIN3 GPIO1[10]/GTM1_TGATE4/ GTM2_TGATE3 GPIO1[11]/GTM1_TOUT4/ GTM2_TOUT3 E24 B25 D24 A25 B24 A24 D23 B23 A23 F22 E22 USB Port 1 MPH1_D0_ENABLEN/ DR_D0_ENABLEN MPH1_D1_SER_TXD/ DR_D1_SER_TXD MPH1_D2_VMO_SE0/ DR_D2_VMO_SE0 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM MPH1_D6_SER_RCV/ DR_D6_SER_RCV MPH1_D7_DRVVBUS/ DR_D7_DRVVBUS MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT A26 B26 D25 A27 B27 C27 D26 E26 D27 A28 F26 E27 I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 59 Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal MPH1_PCTL0/DR_TX_VALID_PCTL0 A29 Package Pin Number Pin Type O O I USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS MPH0_D2_VMO_SE0/DR_D10_DPPD MPH0_D3_SPEED/DR_D11_DMMD MPH0_D4_DP/DR_D12_VBUS_VLD MPH0_D5_DM/DR_D13_SESS_END MPH0_D6_SER_RCV/DR_D14 MPH0_D7_DRVVBUS/ DR_D15_IDPULLUP MPH0_NXT/DR_RX_ACTIVE_ID MPH0_DIR_DPPULLUP/DR_RESET MPH0_STP_SUSPEND/ DR_TX_READY MPH0_PWRFAULT/DR_RX_VALIDH MPH0_PCTL0/DR_LINE_STATE0 MPH0_PCTL1/DR_LINE_STATE1 MPH0_CLK/DR_RX_VALID C29 A30 E28 B30 C30 A31 B31 C31 B32 A32 A33 C32 D31 E30 B33 Programmable Interrupt Controller MCP_OUT IRQ0/MCP_IN/GPIO2[12] IRQ[1:5]/GPIO2[13:17] IRQ[6]/GPIO2[18]/CKSTOP_OUT IRQ[7]/GPIO2[19]/CKSTOP_IN AN33 C19 C22, A22, D21, C21, B21 A21 C20 Ethernet Management Interface EC_MDC EC_MDIO A7 E9 Gigabit Reference Clock EC_GTX_CLK125 C8 I LVDD1 O I/O LVDD1 LVDD1 2 O I/O I/O I/O I/O OV DD OV DD OV DD OV DD OV DD 2 I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I/O I/O I OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Power Supply OV DD OV DD OV DD Notes MPH1_PCTL1/DR_TX_VALIDH_PCTL1 D28 MPH1_CLK/DR_CLK B29 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 60 Freescale Semiconductor Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal Package Pin Number Pin Type Power Supply Notes Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[26] TSEC1_RXD[7:4]/GPIO2[22:25] TSEC1_RXD[3:0] TSEC1_TX_CLK TSEC1_TXD[7:4]/GPIO2[27:30] TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER/GPIO2[31] A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 E10, A8, F10, B8 D17 A15, B15, A14, B14 A10, E11, B10, A9 B9 A16 Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_COL/GPIO1[21] TSEC2_CRS/GPIO1[22] TSEC2_GTX_CLK TSEC2_RX_CLK TSEC2_RX_DV/GPIO1[23] TSEC2_RXD[7:4]/GPIO1[26:29] TSEC2_RXD[3:0]/GPIO1[13:16] TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/ DR_XCVR_TERM_SEL TSEC2_TXD[5]/ DR_UTMI_OPMODE1 TSEC2_TXD[4]/ DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] C14 D6 A4 B4 E6 A13, B13, C13, A12 D7, A6, E8, B7 D14 B12 C12 D12 E12 B5, A5, F8, B6 F14 C5 I/O I/O O I I/O I/O I/O I/O I/O O O O I/O I/O I/O OV DD LVDD2 LVDD2 LVDD2 LVDD2 OV DD LVDD2 OV DD OV DD OV DD OV DD OV DD LVDD2 OV DD LVDD2 3 I/O I/O O I I I/O I/O I I I/O O O I/O OV DD LVDD1 LVDD1 LVDD1 LVDD1 OV DD OVDD LVDD1 OV DD OV DD LVDD1 LVDD1 OV DD 3 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 61 Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal TSEC2_TX_CLK/GPIO1[30] E14 DUART UART_SOUT[1:2]/MSRCID[0:1]/ LSRCID[0:1] UART_SIN[1:2]/MSRCID[2:3]/ LSRCID[2:3] UART_CTS[1]/MSRCID4/LSRCID4 UART_CTS[2]/MDVAL/ LDVAL UART_RTS[1:2] AK27, AN29 AL28, AM29 AP30 AN30 AP31, AM30 I C interface IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL AK29 AP32 AN31 AM31 SPI SPIMOSI SPIMISO SPICLK SPISEL AN32 AP33 AK30 AL31 Clocks PCI_CLK_OUT[0:7] PCI_SYNC_IN/PCI_CLOCK PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN AN9, AP9, AM10, AN10, AJ11, AP10, AL11, AM11 AK12 AP11 AM32 AM9 JTAG TCK TDI TDO TMS TRST E20 F20 B20 A20 B19 I I O I I OV DD OV DD OV DD OV DD OV DD 4 3 4 4 O I O I I OV DD OV DD OV DD OV DD OV DD 3 I/O I/O I/O I OV DD OV DD OV DD OV DD I/O I/O I/O I/O OV DD OV DD OV DD OV DD 2 2 2 2 2 Package Pin Number Pin Type I/O Power Supply OV DD Notes O I/O I/O I/O O OV DD OV DD OV DD OV DD OV DD MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 62 Freescale Semiconductor Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal Package Pin Number Test TEST TEST_SEL D22 AL13 PMC QUIESCE A18 System Control PORESET HRESET SRESET C18 B18 D18 Thermal Management THERM0 K32 Power and Ground Signals AVDD1 AVDD2 L31 AP12 Power for e300 PLL (1.2 )V) Power for system PLL (1.2 V)) Power for DDR DLL (1.2 V)) Power for LBIU DLL (1.2 V)) -- AV DD1 AV DD2 I -- 9 I I/O I/O OV DD OV DD OV DD 1 2 O OV DD I I OV DD OV DD 6 7 Pin Type Power Supply Notes AVDD3 AVDD4 GND AE1 AJ13 A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, E15, E17, E18, E21, E23, E25, E32, F6, F19, F27, F30, F34, G31, H5, J4, J34, K30, L5, M2, M5, M30, M33, N3, N5, P30, R5, R32, T5, T30, U6, U29, U33, V2, V5, V30, W6, W30, Y30, AA2, AA30, AB2, AB6, AB30, AC3, AC6, AD31, AE5, AF2, AF5, AF31, AG30, AG31, AH4, AJ3, AJ19, AJ22, AK7, AK13, AK14, AK16, AK18, AK20, AK25, AK28, AL3, AL5, AL10, AL12, AL22, AL27, AM1, AM6, AM7, AN12, AN17, AN34, AP1, AP8, AP34 A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, R6, T6, U5, V1, W5, Y5, AA4, AB3, AC4, AD5, AF3, AG5, AH2, AH5, AH6, AJ6, AK6, AK8, AK9, AL6 AV DD3 AV DD4 -- GV DD Power for DDR DRAM I/O voltage (2.5 V) GVDD MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 63 Package and Pin Listings Table 51. MPC8349E (TBGA) Pinout Listing (continued) Signal LVDD1 C9, D11 Package Pin Number Pin Type Power for three speed Ethernet #1 and for Ethernet management interface I/O (2.5 V, 3.3 V) Power for three speed Ethernet #2 I/O (2.5 V, 3.3 V) Power for core (1.2 V) Power Supply LVDD1 Notes LVDD2 C6, D9 LVDD2 VDD E19, E29, F7, F9, F11,F13, F15, F17, F18, F21, F23, F25, F29, H29, J6, K29, M29, N6, P29, T29, U30, V6, V29, W29, AB29, AC5, AD29, AF6, AF29, AH29, AJ8, AJ12, AJ14, AJ16, AJ18, AJ20, AJ21, AJ23, AJ25, AJ26, AJ27, AJ28, AJ29, AK10 B22, B28, C16, C17, C24, C26, D13, D15, D19, D29, E31, F28, G33, H30, L29, L32, N32, P31, R31, U32, W31, Y29, AA29, AC30, AE31, AF30, AG29, AJ17, AJ30, AK11, AL15, AL19, AL21, AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13 M3 VDD OVDD PCI, 10/100 Ethernet, and other standard (3.3 V) OV DD MVREF1 I DDR reference voltage DDR reference voltage MVREF2 AD2 I Notes: 1. This pin is an open-drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OV DD. 2. This pin is an open-drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. During reset, this output is actively driven rather than three-stated. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications. 6. This pin must always be tied to GND. 7. This pin must always be pulled up to OV DD. 8. This pin must always be left not connected. 9. Thermal sensitive resistor. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 64 Freescale Semiconductor Clocking 19 Clocking Figure 39 shows the internal distribution of the clocks. MPC8349E e300 Core Core PLL core_clk csb_clk System PLL To DDR Memory Controller DDR Clock ddr_clk Div /2 Clock Unit lbiu_clk /n To Local Bus Memory LBIU Controller DLL 6 6 MCK[0:5] MCK[0:5] DDR Memory Device LCLK[0:2] LSYNC_OUT LSYNC_IN Local Bus Memory Device csb_clk to Rest of the Device CFG_CLKIN_DIV CLKIN PCI Clock Divider 8 PCI_CLK/ PCI_SYNC_IN PCI_SYNC_OUT PCI_CLK_OUT[0:7] Figure 39. MPC8349E Clock Subsystem The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8349E is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (/2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the MPC8349E to function. When the MPC8349E is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 65 Clocking As shown in Figure 39, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF In PCI host mode, PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349E Reference Manual for more information on the clock subsystem. The internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk x (1 + RCWL[DDRCM]) ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (/2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk x (1 + RCWL[LBIUCM]) lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is controlled by LCCR[CLKDIV]. In addition, some of the internal units may have to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped register after the device exits reset. Table 52 specifies which units have a configurable clock frequency. Table 52. Configurable Clock Units Unit TSEC1 TSEC2, I2C1 Default Frequency Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3 csb_clk Security core USB DR, USB MPH PCI1, PCI2 and DMA complex MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 66 Freescale Semiconductor Clocking Table 53 provides the operating frequencies for the MPC8349E TBGA under recommended operating conditions (see Table 2). Table 53. Operating Frequencies for TBGA Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR memory bus frequency (MCK)2 Local bus frequency (LCLKn)3 PCI input frequency (CLKIN or PCI_CLK) Security core maximum internal operating frequency USB_DR, USB_MPH maximum internal operating frequency 1 400 MHz 266-400 100-266 100-133 16.67-133 25-66 133 133 533 MHz 266-533 100-333 100-133 16.67-133 25-66 133 133 667 MHz 266-667 100-333 100-166.67 16.67-133 25-66 166 166 Unit MHz MHz MHz MHz MHz MHz MHz The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]). 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 54 shows the multiplication factor encodings for the system PLL. Table 54. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 System PLL Multiplication Factor x 16 Reserved x2 x3 x4 x5 x6 x7 x8 x9 x 10 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 67 Clocking Table 54. System PLL Multiplication Factors (continued) RCWL[SPMF] 1011 1100 1101 1110 1111 System PLL Multiplication Factor x 11 x 12 x 13 x 14 x 15 As described in Section 19, "Clocking," the LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 55 and Table 56 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 68 Freescale Semiconductor Clocking Table 55. CSB Frequency Options for Host Mode Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at Reset1 SPMF csb_clk : Input Clock Ratio2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High High High High High High High 1 2 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 0110 0111 1000 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 2:1 3:1 4:1 5:1 6:1 7:1 8:1 100 133 166 200 233 100 116 133 150 166 183 200 216 233 250 266 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333 133 200 266 333 133 200 266 333 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 69 Clocking Table 56. CSB Frequency Options for Agent Mode Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at Reset1 SPMF csb_clk : Input Clock Ratio2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High High High High High High High 1 2 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 0110 0111 1000 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 4:1 6:1 8:1 10 : 1 12 : 1 14 : 1 16 : 1 100 133 166 200 233 266 100 116 133 150 166 183 200 216 233 250 266 100 150 200 250 300 133 200 266 333 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333 133 200 266 333 266 CFG_CLKIN_DIV doubles csb_clk if set high. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. 19.2 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 57 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 57 should be considered as reserved. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 70 Freescale Semiconductor Clocking NOTE Core VCO frequency = core frequency x VCO divider VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz. Table 57. e300 Core PLL Configuration RCWL[COREPLL] core_clk : csb_clk Ratio 0-1 nn 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 1 VCO Divider1 2-5 0000 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 6 n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 PLL bypassed (PLL off, csb_clk clocks core directly) 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 PLL bypassed (PLL off, csb_clk clocks core directly) 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 8 Core VCO frequency = core frequency x VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz. 19.3 Suggested PLL Configurations Table 58 shows suggested PLL configurations for 33 and 66 MHz input clocks. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 71 Clocking Table 58. Suggested PLL Configurations Ref No.1 RCWL 400 MHz Device Input Clock Freq (MHz)2 533 MHz Device Input Clock Freq (MHz)2 667 MHz Device Input Clock Freq (MHz)2 SPMF CORE PLL CSB Freq (MHz) Core Freq (MHz) CSB Freq (MHz) Core Freq (MHz) CSB Freq (MHz) Core Freq (MHz) 33 MHz CLKIN/PCI_CLK Options 922 723 604 624 803 823 903 923 704 724 A03 804 705 606 904 805 A04 1001 0111 0110 0110 1000 1000 1001 1001 0111 0111 1010 1000 0111 0110 1001 1000 1010 0100010 0100011 0000100 0100100 0000011 0100011 0000011 0100011 0000011 0100011 0000011 0000100 0000101 0000110 0000100 0000101 0000100 -- 33 33 33 33 33 -- 233 200 200 266 266 -- -- -- -- -- -- -- -- -- -- -- 33 33 33 -- 350 400 400 400 400 -- 33 33 33 33 33 -- 233 200 200 266 266 -- -- 233 233 -- 266 -- -- -- -- -- 533 466 466 300 350 400 400 400 400 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 300 233 200 200 266 266 300 300 233 233 333 266 233 200 300 266 333 300 350 400 400 400 400 450 450 466 466 500 533 583 600 600 667 667 66 MHz CLKIN/PCI_CLK Options 304 324 403 423 305 503 404 306 405 504 1 0011 0011 0100 0100 0011 0101 0100 0011 0100 0101 0000100 0100100 0000011 0100011 0000101 0000011 0000100 0000110 0000101 0000100 66 66 66 66 200 200 266 266 -- -- -- -- -- -- 400 400 400 400 66 66 66 66 66 200 200 266 266 200 -- 400 400 400 400 500 66 66 66 66 66 66 200 200 266 266 200 333 266 200 266 333 400 400 400 400 500 500 533 600 667 667 66 266 -- -- -- 533 66 66 66 66 The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4-15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 72 Freescale Semiconductor Thermal 20 Thermal This section describes the thermal specifications of the MPC8349E. 20.1 Thermal Characteristics Table 59. Package Thermal Characteristics for TBGA Characteristic Symbol RJA RJMA RJMA RJMA RJMA RJMA RJB RJC JT Value 14 11 11 8 9 7 3.8 1.7 1 Unit C/W C/W C/W C/W C/W C/W C/W C/W C/W Notes 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 4 5 6 Table 59 provides the package thermal characteristics for the 672 35 x 35 mm TBGA of the MPC8349E. Junction-to-ambient natural convection on single-layer board (1s) Junction-to-ambient natural convection on four-layer board (2s2p) Junction-to-ambient (@ 200 ft/min) on single-layer board (1s) Junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p) Junction-to-ambient (@ 2 m/s) on single-layer board (1s) Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) Junction-to-board thermal Junction-to-case thermal Junction-to-package natural convection on top Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM). 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 20.2 Thermal Management Information For the following sections, PD = (VDD x IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 5 for I/O power dissipation values. 20.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 73 Thermal where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single-layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible. 20.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 20.2.3 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (JT) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TJ = junction temperature (C) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 74 Freescale Semiconductor Thermal TT = thermocouple temperature on top of package (C) JT = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 20.2.4 Heat Sinks and Junction-to-Case Thermal Resistance Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Table 60 shows heat sink thermal resistance for TBGA of the MPC8349E. Table 60. Heat Sink and Thermal Resistance of MPC8349E (TBGA) 35 x 35 mm TBGA Heat Sink Assuming Thermal Grease AAVID 30 x 30 x 9.4 mm pin fin AAVID 30 x 30 x 9.4 mm pin fin AAVID 30 x 30 x 9.4 mm pin fin AAVID 31 x 35 x 23 mm pin fin AAVID 31 x 35 x 23 mm pin fin AAVID 31 x 35 x 23 mm pin fin Air Flow Thermal Resistance Natural convection 1 m/s 2 m/s Natural convection 1 m/s 2 m/s 10 6.5 5.6 8.4 4.7 4 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 75 Thermal Table 60. Heat Sink and Thermal Resistance of MPC8349E (TBGA) (continued) 35 x 35 mm TBGA Heat Sink Assuming Thermal Grease Wakefield, 53 x 53 x 25 mm pin fin Wakefield, 53 x 53 x 25 mm pin fin Wakefield, 53 x 53 x 25 mm pin fin MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 mm, adjacent board, 40 mm side bypass Air Flow Thermal Resistance Natural convection 1 m/s 2 m/s Natural convection 1 m/s 2 m/s 1 m/s 5.7 3.5 2.7 6.7 4.1 2.8 3.1 Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com 603-224-9988 408-567-8082 818-842-7277 408-436-8770 800-522-2800 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 76 Freescale Semiconductor Thermal Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 603-635-5102 781-935-4850 800-248-2481 888-642-7674 800-347-4572 20.3 Heat Sink Attachment When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements. 20.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 77 Thermal TJ = TC + (RJC x PD) where: TJ = junction temperature (C) TC = case temperature of the package (C) RJC = junction-to-case thermal resistance (C/W) PD = power dissipation (W) MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 78 Freescale Semiconductor System Design Information 21 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8349E. 21.1 System Clocking The MPC8349E includes two PLLs: 1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 19.1, "System PLL Configuration." 2. The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 19.2, "Core PLL Configuration." 21.2 PLL Power Supply Filtering Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD level should always equal to VDD, and preferably these voltages are derived directly from V DD through a low frequency filter scheme. There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 40, one to each of the five AVDD pins. Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other. The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 40 shows the PLL power supply filter circuit. 10 V DD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD (or L2AV DD) GND Figure 40. PLL Power Supply Filter Circuit MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 79 System Design Information 21.3 Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8349E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8349E system, and the MPC8349E itself requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the MPC8349E. These capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Others can surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, distribute several bulk storage capacitors around the PCB, feeding the V DD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100-330 F (AVX TPS tantalum or Sanyo OSCON). 21.4 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the MPC8349E. 21.5 Output Buffer DC Impedance The MPC8349E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 41). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 80 Freescale Semiconductor System Design Information OV DD RN SW2 Data Pad SW1 RP OGND Figure 41. Driver Impedance Measurement Two measurements give the value of this resistance and the strength of the driver current source. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = (1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105C. Table 61. Impedance Characteristics Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target NA PCI Signals (Not Including PCI Output Clocks) 25 Target 25 Target NA PCI Output Clocks (Including PCI_SYNC_OUT) 42 Target 42 Target NA Impedance DDR DRAM Symbol Unit RN RP Differential 20 Target 20 Target NA Z0 Z0 ZDIFF Note: Nominal supply voltages. See Table 1, Tj = 105C. 21.6 Configuration Pin Multiplexing The MPC8349E power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 k on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation. However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 81 System Design Information the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for the output pins. 21.7 Pull-Up Resistor Requirements The MPC8349E requires high resistance pull-up resistors (10 k is recommended) on open-drain pins, including I2C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, refer to application note AN2931, PowerQUICCTM Design Checklist. MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 82 Freescale Semiconductor Document Revision History 22 Document Revision History Table 62 provides a revision history of this document. Table 62. Document Revision History Revision 10 Date 4/2007 Substantive Change(s) In Table 3, "Output Drive Capability," changed the values in the Output Impedance column and added USB to the seventh row. In Section 21.7, "Pull-Up Resistor Requirements," deleted last two paragraphs and after first paragraph, added a new paragraph. Deleted Section 21.8, "JTAG Configuration Signals," and Figure 43, "JTAG Interface Connection." In Table 53, "Operating Frequencies for TBGA," in the `Coherent system bus frequency (csb_clk)' row, changed the value in the 533 MHz column to 100-333. In Table 58, "Suggested PLL Configurations," under the subhead, `33 MHz CLKIN/PCI_CLK Options,' added row A03 between Ref. No. 724 and 804. Under the subhead `66 MHz CLKIN/PCI_CLK Options,' added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed the CORE PLL value to 0000110. In Section 23, "Ordering Information," replaced first paragraph and added a note. In Section 23.1, "Part Numbers Fully Addressed by This Document," replaced first paragraph. Page 1, updated first paragraph to reflect PowerQUICC II Pro information. Updated note after second paragraph. In the features list in Section 1, "Overview," corrected DDR data rate to show: * 333 MHz for DDR for TBGA parts for silicon Rev. 1.x In Figure 42, "JTAG Interface Connection," updated with new figure. In Section 23, "Ordering Information," replicated note from introduction. In Section 23.1, "Part Numbers Fully Addressed by This Document," replaced third sentence of first paragraph directing customer to product summary page for available frequency configuration parts. Updated back page information. Changed all references to revision 2.0 silicon to revision 3.0 silicon. Changed VIH minimum value in Table 40, "JTAG Interface DC Electrical Characteristics," to OVDD - 0.3. In Table 66, "Suggested PLL Configurations," deleted reference-number rows 902 and 703. Section 2, "Electrical Characteristics," moved to second section and all other section, table, and figure numbering change accordingly. Table 8, "CLKIN AC Timing Specifications:" Changed max rise and fall time from 1.2 to 2.3. Table 26, "GMII Receive AC Timing Specifications:" Changed min tTTKHDX from 0.5 to 1.0. Table 34, "MII Management AC Timing Specifications:" Changed max value of tMDKHDX from 70 to 170. Table 38, "Local Bus General Timing Parameters--DLL on:" Changed min tLBIVKH2 from 1.7 to 2.2. Table 40, "JTAG interface DC Electrical Characteristics:" Changed VIH input high voltage min to 2.0. Table 51, "Operating Frequencies for TBGA:" * Updated TBD values. * Changed maximum coherent system bus frequency for TBGA 533-MHz device to 266. Added Section 23.2, "Part Marking." Table 58, "Suggested PLL Configurations:" Removed some values from suggested PLL configurations for reference numbers 902, 922, 903, and 923. Table 65, "Part Numbering Nomenclature:" Updated TBD values in note 1. Added Table 66 "SVR Settings." 9 3/2007 8 2/2007 7 8/2006 6 3/2006 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 83 Document Revision History Table 62. Document Revision History (continued) Revision 5 Date 10/2005 Substantive Change(s) Table 63: Updated AAVID 30x30x9.4 mm Pin Fin (natural convection) junction-to-ambient thermal resistance, from 11 to 10. Changed classification of document to `Technical Data.' Added Table 2, "MPC8349E Typical I/O Power Dissipation." Table 1: Updated values for power dissipation that were TBD in Revision 2. Table 1: Typical values for power dissipation are changed to `TBD.' Table 1: Addition of note 1. Table 51: Addition of Therm0 (K32). Initial release. 4 3 2 1 0 9/2005 8/2005 5/2005 4/2005 4/2005 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 84 Freescale Semiconductor Ordering Information 23 Ordering Information This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked. NOTE The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and later versions (orderable part numbers ending with A or B), see the MPC8349EA PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications (Document Order No. MPC8349EAEC). 23.1 Part Numbers Fully Addressed by This Document Table 63 shows an analysis of the Freescale part numbering nomenclature for the MPC8349E. The individual part numbers correspond to a maximum processor core frequency. Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the MPC8349E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. Table 63. Part Numbering Nomenclature MPC nnnn Product Part Code Identifier MPC 8349 e Encryption Acceleration Blank = Not included E = included t Temperature1 Range Blank = 0 to 105C C = -40 to 105C pp Package2 ZU =TBGA VV = PB free TBGA aa Processor Frequency3 e300 core speed AG = 400 AJ = 533 AL = 667 a Platform Frequency D = 266 F = 333 r Revision Level Blank = 1.1 or 1.0 Notes: 1. For temperature range = C, processor frequency is limited to 400 with a platform frequency of 266. 2. See Section 18, "Package and Pin Listings," for more information on available package types. 3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. Table 64 shows the SVR settings by device and package type. Table 64. SVR Settings Device MPC8349E MPC8349 Package TBGA TBGA SVR (Rev. 1.0) 8050_0010 8051_0010 MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 85 Ordering Information 23.2 Part Marking Parts are marked as in the example shown in Figure 42. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ TBGA Notes: ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code. Figure 42. Freescale Part Marking for TBGA Devices MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 86 Freescale Semiconductor Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8349E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 87 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. IEEE 802.11i, 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, and 1149.1 are trademarks or registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2005-2007. All rights reserved. Document Number: MPC8349EEC Rev. 10 07/2007 |
Price & Availability of MPC8349E07
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |